1. Field of the Invention
The present invention relates to a charge transfer device (CTD) having a charge detecting portion of a floating diffusion amplifier type (hereinafter, referred to as xe2x80x9cFDA typexe2x80x9d) preferable for an image sensor, a delay device, etc. More specifically, the present invention relates to a charge transfer device which is capable of decreasing a reset gate voltage in a charge voltage converting portion of a signal charge, realizing non-adjustment of a reset gate voltage, and thereby reducing the number of components in a system and power consumption.
2. Description of the Related Art
As a representative device using a CTD such as a charge coupled device (CCD), a two-dimensional image sensor shown in FIG. 7, a delay device of a serial-parallel-serial (SPS) system shown in FIG. 8, and the like are well-known.
In the two-dimensional image sensor shown in FIG. 7, a signal charge photoelectrically converted by photoelectric conversion elements 2 arranged in a matrix is transferred to a signal output portion 12 via a vertical transfer channel 6 and a horizontal transfer channel 8. The transferred signal charge is charge-voltage converted at the signal output portion 12 and given to an amplifier (MOS amplifier) 14. When the amplifier 14 is operated, an output signal is taken out. Thereafter, when a reset transistor (not shown) is operated, the signal output portion 12 is reset to a reference level VRD (power-supply voltage). Reference numeral 4 denotes a transfer gate.
In the delay device shown in FIG. 8, a signal charge given to a signal input portion 16 from an input terminal is transferred to a signal output portion 12 via a horizontal transfer channel 18, a vertical transfer channel 6, and a horizontal transfer channel 8. Thereafter, an operation similar to that of the image sensor shown in FIG. 7 is operated.
An example of a charge transfer device includes one which is provided with an FDA type charge detecting portion. FIG. 9 shows a representative structural example of an FDA type charge detecting portion. This charge detecting portion includes a reset drain (RD) 22, a reset gate (RG) 20, an output gate (OG), a horizontal transfer gate 8 consisting of H1, H2, . . . , a floating diffusion (FD), and an amplifier (MOS amplifier) 14. The reset drain 22 and the floating diffusion (FD) are a N+ region formed in a p-type semiconductor substrate. The floating diffusion (FD) and the p-type semiconductor substrate are collectively referred to as a floating diode 24.
FIG. 10 shows a drive timing of the charge detecting portion. FIG. 11 is a diagram showing a potential relationship between the time and the potential. FIG. 12 shows (VGxe2x88x92"PHgr"max) characteristics.
Herein, V"PHgr"RLow and V"PHgr"RHigh represent a xe2x80x9cLowxe2x80x9d level and a xe2x80x9cHighxe2x80x9d level of a reset pulse applied to the reset gate 20, as shown in FIG. 10. xcex94Vmax in FIG. 11 represents the maximum signal amplitude that can be handled by the floating diode 24.
Assuming that a potential under the reset gate 20 is "PHgr"max (VG[V]) and a voltage applied to the reset drain 22 is VRD, xcex94Vmax is represented by the following Expression (1):
xcex94Vmax=VRDxe2x88x92"PHgr"max(V"PHgr"RLow)xe2x88x92xcex94VFxe2x80x83xe2x80x83(1)
wherein xcex94VF represents a field-through component of a signal output.
From the above expression, in order to perform a reset operation of the reset gate 20, the following Expression (2) should be satisfied.
"PHgr"max(V"PHgr"RHigh)xe2x88x92VRDxe2x89xa70xe2x80x83xe2x80x83(2)
Furthermore, in the case where a reset gate pulse at a predetermined level is applied to the reset gate 20 from outside (outside of a device), when "PHgr"max and the voltage VRD applied to the reset drain 22 are under a predetermined condition, an amplitude and a level of a required reset gate pulse are, for example, as follows: in the case of VRD=15.0 V, "PHgr"max(VG=0 V)=8.9 V, xcex94"PHgr"max/xcex94VG=0.8, and xcex94VF=0.75 V, in order to satisfy xcex94Vmaxxe2x89xa71.2 V, the following Expression (3) should be satisfied:
V"PHgr"RLowxe2x89xa65.1 Vxe2x80x83xe2x80x83(3)
and in order to ensure a reset operation, the following Expression (4) should be satisfied:
V"PHgr"RHighxe2x89xa77.6 Vxe2x80x83xe2x80x83(4).
Thus, if an amplitude of a reset pulse is at least 2.5 V (=7.6 Vxe2x88x925.1 V), a reset operation can be ensured.
However, there are in actuality variations in a potential under the reset gate 20 and in a power-supply voltage used in such a system due to the variations in the production processes of a device. Therefore, it is required to set an amplitude and a level of a reset gate pulse so as to simultaneously ensure xcex94Vmax and a reset operation, considering each variation.
As an example, FIG. 13 shows (VGxe2x88x92"PHgr"max) characteristics of the reset gate 20 in the case where the variation of the potential "PHgr"max is xc2x10.7 V, and the variation of the voltage VRD to be applied to the reset drain 22 is xc2x10.5 V.
Under the conditions of VRD=15.0xc2x10.5 V, "PHgr"max(VG=0 V)=8.9xc2x10.7 V, xcex94"PHgr"max/xcex94VG=0.8, and xcex94VF=0.75 V, in order to satisfy xcex94Vmaxxe2x89xa71.2 V, the following Expression (5) should be satisfied:
V"PHgr"RLowxe2x89xa63.6 Vxe2x80x83xe2x80x83(5)
and in order to ensure a reset operation, the Expression (6) should be satisfied:
V"PHgr"RHighxe2x89xa79.1 Vxe2x80x83xe2x80x83(6)
Thus, an amplitude of a reset pulse should be at least 5.5 V (=9.1 Vxe2x88x923.6 V).
A variation of xc2x10.7 V of the potential "PHgr"max corresponds to a reset pulse width of 1.75 V, and a variation of xc2x10.5 V of the voltage VRD applied to the reset drain 22 corresponds to a reset pulse width of 1.25 V. Therefore, a reset pulse width is required to be 3.0 V (=1.75 V+1.25 V) plus 2.5 V (=7.6 Vxe2x88x925.1 V; in the case of no variations).
Recently, for example, in a two-dimensional image sensor, there is a demand for a decrease in the drive voltage and in the number of components, in addition to the demand for further miniaturization of a device and reductions in power consumption.
In the past, an output from a timing IC is amplified by an external circuit, offset, and input to a device as a pulse applied to a reset gate of an FDA type charge detecting portion. Due to the demand for a decrease in the drive voltage, a reduction in the number of components of a system, and a reduction in power consumption, driving of a reset gate with a voltage of 3.3 V, a decrease in the drive voltage, and non-adjustment of an offset voltage are in demand.
However, in a conventional system in which a reset gate pulse at a predetermined level is applied from the outside, an offset voltage of a reset pulse is required to be applied and adjusted by an external circuit. Furthermore, regarding decreases in voltage, it is required to consider the variation (+0.7 V in FIG. 13) of a potential under a reset gate and the variation (xc2x10.5 V in FIG. 13) of a voltage applied to a reset drain due to the variations of a process. This involves difficulty in control, so that sufficient Vmax and a reset operation cannot be ensured.
In order to overcome these problems, there is a method for obtaining an optimum point of a reset operation in the course of a wafer test and writing the measured value into a write circuit provided in a device. However, according to this method, a wafer test and a method for writing a measured value become undesirably complicated.
Another method is described in Japanese Laid-Open Publication No. 6-133227. According to this method, as shown in FIG. 14, a control circuit including a detecting transistor 51 having the same potential profile as that of a reset gate 20 of an FDA type charge detecting portion A is provided in a device, and fluctuation in a reset operation point caused by the fluctuation in potential under the reset gate 20 is controlled by a detected value of a control circuit.
More specifically, a reset drain 22, a gate for detection, and a gate voltage for detection are used to reset a voltage of the reset drain 22.
However, according to this method, there are the following problems: (1) a pulse applied to the reset gate 20 is not varied in accordance with a voltage applied to the reset drain 22, so that the variation in each voltage should be considered; (2) a DC voltage applied to a gate of the detecting transistor 51 is not varied in accordance with a voltage applied to a drain of the detecting transistor 51, so that the variation in each voltage should be considered; and (3) a voltage of a floating diode 24 to be reset is affected by a voltage VRD of the reset drain 22; however, the voltage VRD of the reset drain 22 becomes unstable due to the induction of an external pulse and the heat emission of carriers.
Another method is described in Japanese Laid-Open Publication No. 4-360544. According to this method, as shown in FIG. 15, a detecting transistor 51 is combined with an inversion amplifier 56 in which a voltage gain is matched with an inverse number of a gradient of "PHgr"max vs. VG of a reset gate 20 of a charge detecting portion A, and an inverted voltage corresponding to a potential under the gate of the detecting transistor 51 is applied to the reset gate 20.
However, according to this method, an output of the detecting transistor 51 is directly input to the gate of the inversion amplifier 56. Therefore, the input signal to the charge detecting portion A includes unstable elements such as the induction of an external pulse and the heat emission of carriers. Furthermore, according to this method, the reset voltage is not corrected, so that the reset voltage may be unstable. Therefore, the above-mentioned problem will not be overcome by this method.
As described above, there are no conventional CTDs in which a satisfactory reset operation, a decrease in a reset gate voltage, and non-adjustment of a reset gate voltage are simultaneously achieved, whereby a reduction in the number of components in a system and a decrease in power consumption are realized.
A charge transfer device of the present invention includes: a floating diffusion amplifier type charge detecting portion containing a reset gate and a reset drain; and a source follower circuit including a detecting transistor having substantially the same potential profile as a potential profile of the reset gate of the charge detecting portion and a load transistor connected to the detecting transistor, wherein an output from the source follower circuit is supplied to the reset drain of the charge detecting portion, a first voltage, which is generated by resistance-dividing a power-supply voltage to be supplied to a drain of the source follower circuit, is commonly applied to each gate of the detecting transistor and the load transistor, a second voltage, which is generated by resistance-dividing the power-supply voltage, is applied to the reset gate of the charge detecting portion via a clamp circuit, whereby the charge transfer device is controlled in such a manner that a reset operation is always performed in an optimum state, irrespective of a variation in a potential under the reset gate.
A charge transfer device of the present invention includes a floating diffusion amplifier type charge detecting portion and a control circuit including a detecting transistor having substantially the same potential profile as a potential profile of a reset gate of the charge detecting portion provided in the device, the charge transfer device being controlled in such a manner that a reset operation is always performed in an optimum state, irrespective of a variation in a potential under the reset gate, wherein the control circuit comprises a source follower circuit including the detecting transistor and an inverter circuit having an input connected to an output of the source follower circuit, a power-supply voltage of the source follower circuit and the inverter circuit is connected to a reset drain of the charge detecting portion, and an output from the inverter circuit is applied to a reset gate of the charge detecting portion via a clamp circuit.
A charge transfer device of the present invention includes: a charge detecting portion including a floating diffusion, a reset gate and a reset drain; a control circuit including a source follower circuit and a resistance divider; and a pulse generating portion, wherein the source follower circuit includes a detecting transistor having substantially the same potential profile as a potential profile of the reset gate of the charge detecting portion and a load transistor connected between a source of the detecting transistor and a ground, and supplies its output to the reset gate together with a pulse generated by the pulse generating portion, and the resistance divider generates a first voltage and a second voltage by resistance-dividing a voltage supplied to a drain of the detecting transistor from a power source, supplies the first voltage commonly to gates of the detecting transistor and the load transistor, and supplies the second voltage to the reset gate.
In one embodiment of the present invention, the control circuit further includes a clamp circuit, and the second voltage is supplied to the reset gate from the resistance divider via the clamp circuit.
A charge transfer device of the present invention includes: a charge detecting portion including a floating diffusion, a reset gate and a reset drain; a control circuit including a source follower circuit and an inverter circuit; and a pulse generating circuit, wherein a voltage supplied from a power source to the reset drain is supplied to the source follower circuit and the inverter circuit as a power-supply voltage, the source follower circuit includes a detecting transistor having substantially the same potential profile as a potential profile of the reset gate of the charge detecting portion, and supplies its output to the inverter circuit, and the inverter circuit supplies a voltage obtained by inverting an output from the source follower circuit to the reset gate together with a pulse generated by the pulse generating portion.
In one embodiment of the present invention, the control circuit further includes a clamp circuit, and the inverted voltage is supplied from the inverter circuit to the reset gate via the clamp circuit.
Hereinafter, the function of the present invention will be described.
The CTD of the present invention includes a charge detecting portion having a floating diffusion, a reset gate, and a reset drain, and a control circuit having a source follower circuit and a resistance divider. The source follower circuit includes a detecting transistor having the same or substantially the same potential profile as that of the reset gate of the charge detecting portion and a load transistor connected between a source of the detecting transistor and a ground, and supplies its output to the reset gate. A resistance divider generates a first voltage and a second voltage by resistance-dividing a voltage supplied from a power source to a drain of the detecting transistor. The resistance divider supplies the first voltage commonly to gates of the detecting transistor and the load transistor, and supplies the second voltage to the reset gate. Therefore, a reset operation can be performed in an optimum state at all times irrespective of variations in a potential under the reset gate, and a satisfactory reset operation, a decrease in a reset gate voltage, and non-adjustment of an offset voltage can be simultaneously achieved. As a result, the number of components in a system and power consumption can be decreased.
Furthermore, if the control circuit further includes a clamp circuit, in which a current flows only in one direction, and the second voltage is supplied from the resistance divider to the reset gate via the clamp circuit, the number of components can be reduced.
Another charge transfer device of the present invention includes a charge detecting portion having a floating diffusion, a reset gate, and a reset drain, and a control circuit having a source follower circuit and an inverter circuit. A voltage supplied from a power source to the reset drain is supplied to the source follower circuit and the inverter circuit as a power-supply voltage. The source follower circuit includes a detecting transistor having the same or substantially the same potential profile as that of the reset gate of the charge detecting portion, and supplies its output to the inverter circuit. The inverter circuit supplies a voltage obtained by inverting the output from the source follower circuit to the reset gate. Therefore, a reset operation can be performed in an optimum state at all times irrespective of variations in a potential under the reset gate, and furthermore, an operation point of an amplifier is not varied.
Furthermore, if the control circuit further includes a clamp circuit, in which a current flows only in one direction, and the above-mentioned inverted voltage is supplied from the inverter circuit to the reset gate via the clamp circuit, the number of components can be reduced.
Thus, the invention described herein makes possible the advantage of providing a CTD in which a satisfactory reset operation, a decrease in a reset gate voltage, and non-adjustment of a reset gate voltage are simultaneously achieved, whereby a reduction in the number of components in a system and a decrease in power consumption are realized.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.